List of Synopsys Starrc Customers
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Since 2010, our global team of researchers has been studying Synopsys Starrc customers around the world, aggregating massive amounts of data points that form the basis of our forecast assumptions and perhaps the rise and fall of certain vendors and their products on a quarterly basis.
Each quarter our research team identifies companies that have purchased Synopsys Starrc for Electromigration Simulation and Design from public (Press Releases, Customer References, Testimonials, Case Studies and Success Stories) and proprietary sources, including the customer size, industry, location, implementation status, partner involvement, LOB Key Stakeholders and related IT decision-makers contact details.
Companies using Synopsys Starrc for Electromigration Simulation and Design include: United Microelectronics Corpora, a Taiwan based Manufacturing organisation with 20000 employees and revenues of $7.05 billion, GlobalFoundries, a United States based Manufacturing organisation with 14000 employees and revenues of $6.79 billion, Altera, a Malaysia based Manufacturing organisation with 2666 employees and revenues of $850.0 million, Semiconductor Manufacturing International (Shanghai) Corporation, a China based Manufacturing organisation with 6500 employees and revenues of $657.0 million and many others.
Contact us if you need a completed and verified list of companies using Synopsys Starrc, including the breakdown by industry (21 Verticals), Geography (Region, Country, State, City), Company Size (Revenue, Employees, Asset) and related IT Decision Makers, Key Stakeholders, business and technology executives responsible for the software purchases.
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| Logo | Customer | Industry | Empl. | Revenue | Country | Vendor | Application | Category | When | SI | Insight |
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Altera | Manufacturing | 2666 | $850M | Malaysia | Synopsys | Synopsys Starrc | Electromigration Simulation and Design | 2012 | n/a |
In 2012, Altera deployed Synopsys Starrc to provide silicon accurate parasitic extraction for its 28 nm Stratix V FPGA designs in the United States. The implementation targeted Electromigration Simulation and Design use cases and was positioned to accelerate signoff and shorten time to market for high performance FPGA designs.
Altera configured Synopsys Starrc for silicon accurate parasitic modeling and extraction workflows, focusing on signoff accurate extraction for the 28 nm node. Functional capabilities implemented included parasitic extraction tuned for advanced node interconnects and electromigration analysis consistent with high performance FPGA signoff requirements.
Operational coverage centered on Stratix V physical design and signoff flows in the United States, with the solution validated in production at the 28 nm process node. The deployment was used directly in signoff release processes to provide production silicon correlation and to support final tapeout quality checks.
Governance and rollout emphasized production validation and signoff accuracy, integrating Synopsys Starrc outputs into Altera engineering signoff workflows. The deployment achieved signoff accurate extraction for high performance FPGA designs and was validated in production for the 28 nm node, enabling the stated objective to accelerate signoff and time to market.
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GlobalFoundries | Manufacturing | 14000 | $6.8B | United States | Synopsys | Synopsys Starrc | Electromigration Simulation and Design | 2018 | n/a |
In 2018, GLOBALFOUNDRIES deployed Synopsys Starrc to support Electromigration Simulation and Design workflows for advanced node qualification. The implementation targeted Eng Design Enablement and Test Chip Design teams in Malta New York and was applied across GF FINFET and FDSOI nodes including 45nm 22nm 14nm 12nm and 7nm, focusing on parasitic extraction and electromigration analysis for custom physical design and test-structure development.
The Synopsys Starrc configuration was used to generate PEX models and perform electro-migration analysis alongside IR drop and current drive checks. Functional use cases documented in engineering records included extracted parasitics for Standard Cell ring oscillators ROFET blocks MRAM and RRAM array pcells Kelvin pad structures and RF amplifier pcells, where extracted data fed transistor level simulation and EM verification workflows.
The deployment integrated Synopsys Starrc outputs with HSPICE and Spectre for circuit simulation Calibre for LVS and sign-off and EMX for electromagnetic analysis as part of the validation chain. Implementation details also show integration with SKILL based PCELL generation and automated placement and routing flows to produce PEX ready layouts and arrays of Kelvin DUTs used for silicon correlation during technology qualification.
Governance emphasized PEX driven sign-off and correlation between extracted models and measured silicon, with StarRC PEX models used to validate resistance and EM behavior against Kelvin structure measurements. Engineering notes record specific validation outcomes including a two orders of magnitude leakage reduction on a 12nm low power ring oscillator when designs were verified using the Synopsys Starrc extraction and downstream simulation chain.
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Semiconductor Manufacturing International (Shanghai) Corporation | Manufacturing | 6500 | $657M | China | Synopsys | Synopsys Starrc | Electromigration Simulation and Design | 2016 | n/a |
In 2016 Semiconductor Manufacturing International Shanghai Corporation standardized on Synopsys StarRC as its signoff parasitic extraction solution for the 28 nm process node. The deployment centered on Synopsys StarRC within SMIC process design kits to support signoff quality parasitic extraction and electromigration analysis, aligning the application to the Electromigration Simulation and Design category.
SMIC integrated StarRC technology files into its PDKs, enabling silicon accurate RC extraction and parasitic netlist generation for both digital and custom design flows. Implementation emphasized signoff parasitic extraction capabilities, technology file management, and process corner aware extraction consistent with Electromigration Simulation and Design functional expectations.
Operational coverage included PDK distribution to mutual customers in China and incorporation of StarRC into signoff flows for chip designers using SMIC 28 nm process technology. The integration focused on ensuring the extraction engine and technology files were embedded in PDK release artifacts used by design and signoff teams.
Governance and rollout involved standardizing on a single parasitic extraction solution across signoff workflows and PDK releases, with PDK-level control of StarRC technology files to maintain consistency for customers. The standardization delivered silicon accurate extraction and improved extraction performance and productivity for digital and custom designs, as stated by SMIC and Synopsys.
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Manufacturing | 20000 | $7.1B | Taiwan | Synopsys | Synopsys Starrc | Electromigration Simulation and Design | 2012 | n/a |
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