List of Siemens Aprisa SoC Design Software Customers
Munich, 80333,
Germany
Since 2010, our global team of researchers has been studying Siemens Aprisa SoC Design Software customers around the world, aggregating massive amounts of data points that form the basis of our forecast assumptions and perhaps the rise and fall of certain vendors and their products on a quarterly basis.
Each quarter our research team identifies companies that have purchased Siemens Aprisa SoC Design Software for Computer-Aided Design (CAD) from public (Press Releases, Customer References, Testimonials, Case Studies and Success Stories) and proprietary sources, including the customer size, industry, location, implementation status, partner involvement, LOB Key Stakeholders and related IT decision-makers contact details.
Companies using Siemens Aprisa SoC Design Software for Computer-Aided Design (CAD) include: MaxLinear, Inc., a United States based Manufacturing organisation with 1503 employees and revenues of $892.0 million, Dolphin Design, a France based Manufacturing organisation with 180 employees and revenues of $25.0 million, Dream Chip Technologies Germany, a Germany based Manufacturing organisation with 150 employees and revenues of $12.0 million, Secafy, a Japan based Professional Services organisation with 30 employees and revenues of $3.0 million and many others.
Contact us if you need a completed and verified list of companies using Siemens Aprisa SoC Design Software, including the breakdown by industry (21 Verticals), Geography (Region, Country, State, City), Company Size (Revenue, Employees, Asset) and related IT Decision Makers, Key Stakeholders, business and technology executives responsible for the software purchases.
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| Logo | Customer | Industry | Empl. | Revenue | Country | Vendor | Application | Category | When | SI | Insight |
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Dolphin Design | Manufacturing | 180 | $25M | France | Siemens | Siemens Aprisa SoC Design Software | Computer-Aided Design (CAD) | 2023 | n/a |
In 2023, Dolphin Design implemented Siemens Aprisa SoC Design Software for Computer-Aided Design (CAD) to support ultra-low-power SoC physical implementation and timing closure. The deployment focused on Dolphin Design’s European SoC implementation teams within the manufacturing organization, targeting physical design closure activities and timing signoff readiness.
Siemens Aprisa SoC Design Software was configured for automated timing closure and physical implementation, emphasizing closure automation that reduced manual engineering change orders. The implementation scope included physical optimization to achieve improved leakage and lower total power, with tool flows tuned to preserve correlation with downstream signoff tools.
Siemens highlighted at User2User 2023 that Aprisa integrated seamlessly into Dolphin Design’s existing physical implementation flow, delivering automated closure and minimizing manual ECOs, and demonstrating excellent correlation with signoff tools. The integration narrative centers on embedding Aprisa into closure workflows to shorten iterative timing cycles and to align implementation results with signoff expectations.
Governance and process changes emphasized shifting closure responsibility into the Aprisa-driven flow, reducing manual ECO-driven rework and standardizing timing closure practices across SoC teams. The case documents a production-focused CAD implementation where Siemens Aprisa SoC Design Software is the focal tool for physical implementation and timing closure within Dolphin Design’s European operations.
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Dream Chip Technologies Germany | Manufacturing | 150 | $12M | Germany | Siemens | Siemens Aprisa SoC Design Software | Computer-Aided Design (CAD) | 2023 | n/a |
In 2023, Dream Chip Technologies Germany deployed Siemens Aprisa SoC Design Software for digital IC physical implementation and place and route on TSMC CLN12FFC projects. The implementation used Siemens Aprisa SoC Design Software as a Computer-Aided Design (CAD) solution to target reduced power consumption and improved turnaround time on advanced node SoC projects in Europe.
The deployment emphasized Aprisa physical implementation and place and route capabilities, with configuration focused on power performance area optimization and strong pre and post route correlation. Integration required minimal setup effort to align Aprisa with Dream Chip's existing implementation flow, and the adjusted flow reduced ECO cycles during late stage routing iterations.
Integration was performed to preserve established verification and tapeout procedures, enabling physical design and SoC implementation teams to adopt Aprisa without large workflow rework. Results and workflow details were presented at Siemens User2User 2023, which documented the integration approach and operational adoption among European design teams.
Reported outcomes from the engagement include reduced power, improved turnaround time, best in class PPA and strong pre and post route correlation on TSMC CLN12FFC projects, along with fewer ECO cycles following integration into Dream Chip's implementation flow.
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MaxLinear, Inc. | Manufacturing | 1503 | $892M | United States | Siemens | Siemens Aprisa SoC Design Software | Computer-Aided Design (CAD) | 2023 | n/a |
In 2023, MaxLinear, Inc. deployed Siemens Aprisa SoC Design Software to support physical design and place-and-route for advanced node development. The Siemens Aprisa SoC Design Software, classified as Computer-Aided Design (CAD), was applied to address aggressive performance, power and closure challenges on 16nm designs and to port flows toward 5nm in the United States.
The implementation centered on physical design flows and place-and-route capabilities, with configuration focused on PPA optimization, closure tuning and tighter timing correlation. Flows were instrumented to reduce engineering change order cycles and to accelerate designer enablement, improving designer productivity for MaxLinear physical design teams. The deployment narrative emphasizes production use on N16 projects while preparing toolchains and scripts for rapid N5 enabling.
Operational rollout reported production status on N16 projects and rapid enabling at N5 as presented at Siemens User2User 2023, reflecting strong timing correlation and reduced ECO cycles. MaxLinear, Inc. Siemens Aprisa SoC Design Software Computer-Aided Design (CAD) supported the companys physical design and place-and-route business functions without external integrator attribution in the disclosed materials.
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Secafy | Professional Services | 30 | $3M | Japan | Siemens | Siemens Aprisa SoC Design Software | Computer-Aided Design (CAD) | 2025 | n/a |
In 2025 Secafy implemented Siemens Aprisa SoC Design Software as the core element of a full IC design flow to develop next-generation hardware security large-scale integration devices. Secafy, a Japan-based hardware security company founded in 2023, adopted Siemens’ portfolio including Aprisa, Solido Simulation Suite, Solido Design Environment, Custom IC Design and Calibre tools, placing this deployment within the Computer-Aided Design (CAD) category and explicitly targeting digital physical-aware synthesis and place-and-route implementations.
The implementation decomposes into functional modules aligned with an end-to-end EDA flow, with Siemens Aprisa SoC Design Software responsible for digital synthesis and physical-aware place-and-route, Solido Simulation Suite and Solido Design Environment providing variability-aware simulation and design centering, Custom IC Design software handling full-custom analog and mixed-signal layout tasks, and Calibre delivering physical verification and rule checking. Configuration leverages toolchain handoffs between synthesis, simulation, layout and signoff phases to support Secafy’s hardware noise evaluation and hardware security analysis workflows, focused on large-scale integration design.
Integration scope covers the engineering and R&D functions responsible for circuit design, implementation and security analysis, with the toolchain applied to device designs targeted at 180nm to 16nm process nodes. The deployment emphasizes data continuity across EDA stages to enable iterative security-focused design validation and to support combined semiconductor security and cryptographic design activities.
Governance centered on standardizing an integrated IC design flow within Secafy’s engineering organization, aligning design review, physical verification and simulation checkpoints to support hardware security objectives. Public statements from Secafy and Siemens indicate the adoption is intended to advance Secafy’s research commercialization and to provide the capabilities needed for their security-focused LSI development.
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