List of ALDEC HES-DVM Customers
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Since 2010, our global team of researchers has been studying ALDEC HES-DVM customers around the world, aggregating massive amounts of data points that form the basis of our forecast assumptions and perhaps the rise and fall of certain vendors and their products on a quarterly basis.
Each quarter our research team identifies companies that have purchased ALDEC HES-DVM for Process Simulation from public (Press Releases, Customer References, Testimonials, Case Studies and Success Stories) and proprietary sources, including the customer size, industry, location, implementation status, partner involvement, LOB Key Stakeholders and related IT decision-makers contact details.
Companies using ALDEC HES-DVM for Process Simulation include: Thales, a France based Aerospace and Defense organisation with 78189 employees and revenues of $22.64 billion, Elbit Systems, a Israel based Aerospace and Defense organisation with 18407 employees and revenues of $5.51 billion, ReneLife India, a India based Life Sciences organisation with 12 employees and revenues of $1.0 million and many others.
Contact us if you need a completed and verified list of companies using ALDEC HES-DVM, including the breakdown by industry (21 Verticals), Geography (Region, Country, State, City), Company Size (Revenue, Employees, Asset) and related IT Decision Makers, Key Stakeholders, business and technology executives responsible for the software purchases.
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| Logo | Customer | Industry | Empl. | Revenue | Country | Vendor | Application | Category | When | SI | Insight |
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Elbit Systems | Aerospace and Defense | 18407 | $5.5B | Israel | ALDEC | ALDEC HES-DVM | Process Simulation | 2014 | n/a |
In 2014, Elbit Systems deployed ALDEC HES-DVM in conjunction with Aldec's DO-254/CTS hardware testing platform to validate multiple FPGAs for a Level A avionics project, operating in Israel. The implementation was positioned within the hardware-emulation/verification category and focused on meeting avionics verification requirements for safety-critical FPGA designs.
The deployment emphasized at-speed FPGA test coverage and DO-254 aligned test suites, using the ALDEC HES-DVM platform to exercise FPGA logic under realistic timing and stimulus conditions. Functional capabilities implemented included automated hardware testbench execution, deterministic test case playback for Level A evidence, and multi-FPGA validation workflows to consolidate verification across device variants.
Operational scope centered on Elbit Systems engineering and verification teams working on the Level A avionics program in Israel, with the verification platform integrated into existing lab test benches and qualification processes. Governance activity for the rollout included preparation and execution of an EASA verification audit, with the ALDEC HES-DVM platform used to generate test artifacts and traceable verification evidence required for certification review.
The implementation supported an increase in at-speed FPGA test coverage and contributed to a reduction in verification risk, outcomes that were validated during the successful EASA verification audit. The result was a structurally stronger FPGA verification posture for Elbit Systems the company, aligning ALDEC HES-DVM hardware-emulation/verification capabilities with avionics certification workflows.
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ReneLife India | Life Sciences | 12 | $1M | India | ALDEC | ALDEC HES-DVM | Process Simulation | 2016 | n/a |
In 2016 ReneLife India partnered with ALDEC to demonstrate its ReneGENE genome-alignment accelerator running on ALDEC HES family FPGA accelerator hardware at SC16, with ALDEC HES-DVM used as the inferred runtime and virtualization layer for the prototype. Apps Category The engagement explicitly positioned ALDEC HES-DVM as the FPGA runtime target for the demonstrator and for accelerating core alignment kernels within ReneGENE.
The technical implementation combined ReneGENE application logic tuned for DNA short read mapping with ALDEC HES-HPC class FPGA boards and the ALDEC HES-DVM software stack, creating a compute architecture that exposed FPGA-accelerated alignment kernels to host research pipelines. Operational scope was an India-based HPC and accelerator demonstration focused on genomics research workflows rather than a production enterprise rollout, integrating ALDEC hardware and software with ReneLife's algorithmic stack. The public showcase at SC16 emphasized the functional capability of ultra-fast DNA short read mapping and validated the use of ALDEC HES family hardware together with ALDEC HES-DVM in a genomics compute context.
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Thales | Aerospace and Defense | 78189 | $22.6B | France | ALDEC | ALDEC HES-DVM | Process Simulation | 2021 | n/a |
In 2021, Thales implemented ALDEC HES-DVM, Apps Category "", to perform hardware verification of a PCIe based avionics FPGA SoC design in France. Thales used ALDEC HES and TLM co emulation capabilities inside ALDEC HES-DVM to exercise FPGA level tests mapped to requirements, enabling 100% FPGA level requirements verification by test. The scope targeted avionics hardware verification workflows executed by engineering teams and aimed to shorten verification cycles.
Deployment centered on co emulation between HES and transaction level modeling to validate PCIe interfaces and system timing, with ALDEC HES-DVM serving as the emulation and test orchestration layer. Functional capabilities implemented included cycle accurate co emulation, stimulus and capture for PCIe transactions, and requirements traceable test execution under ALDEC HES-DVM, integrated into lab based FPGA emulation and test harnesses. Governance emphasized engineering led test plans and requirement to test mapping to support the stated 100% FPGA level verification by test and the abbreviated verification cycles reported.
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