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Michelin, an e2open customer evaluated Oracle Transportation Management

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Moog, an UKG AutoTime customer evaluated Workday Time and Attendance

Wayfair, a Korber HighJump WMS customer just evaluated Manhattan WMS

Westpac NZ, an Infosys Finacle customer evaluated nCino Bank OS

Cantor Fitzgerald, a Kyriba Treasury customer evaluated GTreasury

List of Synopsys DesignWare IP Solutions Customers

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Logo Customer Industry Empl. Revenue Country Vendor Application Category When SI Insight
Achronix Manufacturing 200 $100M United States Synopsys Synopsys DesignWare IP Solutions System on Chip Design 2021 n/a
In 2021 Achronix implemented Synopsys DesignWare IP Solutions as part of its System on Chip Design efforts for high performance 7nm FPGAs. The program targeted Achronix Speedster7t FPGAs, Speedcore eFPGA IP and VectorPath accelerator card designs, aligning IP selection with compute intensive AI, machine learning, networking and data center use cases. The implementation used the DesignWare Foundation and Interface IP suite, including DesignWare Logic Libraries, embedded memory compilers, temperature sensors, PCIe 5.0 IP, and DDR4 PHY and controller IP. The memory compilers enabled creation of over 90 unique memory macros and the DesignWare Logic Libraries were applied to optimize power performance and area with a documented 8% timing improvement. Integration work focused on embedding interface IP into the FPGA SoC fabric and controller stacks, and on aligning PCIe 5.0 and DDR4 PHY implementations with Achronix board level requirements for low latency and high bandwidth. Synopsys technical support was explicitly leveraged to accelerate schedules and to onboard new engineering team members to the 7nm process node and complex interface integrations. Design governance and workflow changes centered on reducing design risk and improving PPA through use of prequalified IP, memory compiler automation, and interface RAS and design for debug capabilities in the DDR4 controller and PCIe 5.0 IP. These practices were incorporated into the engineering design flow to standardize IP configuration, verification handoffs, and debug instrumentation. Results included a two to three month reduction in time to market, measurable area and timing gains from the DesignWare Logic Libraries, and improved latency and bandwidth characteristics from the DesignWare PCIe and DDR IP. Achronix also reported cost avoidance from not developing in house IP and indicated plans to evaluate Synopsys DDR5 IP for future projects.
Axell Corporation Manufacturing 116 $93M Japan Synopsys Synopsys DesignWare IP Solutions System on Chip Design 2015 n/a
In 2015, Axell Corporation implemented Synopsys DesignWare IP Solutions for System on Chip Design. The deployment centered on adoption of Synopsys Design Compiler RTL synthesis capabilities within the Synopsys DesignWare IP Solutions portfolio to support graphics IC design for interactive entertainment and industrial embedded systems. The implementation was intended to target smaller die area and higher engineering productivity through RTL synthesis, area optimized synthesis strategies, standard cell mapping and timing driven optimization. Scope of the implementation was the IC design engineering organization and the core graphics SoC design projects, where the Synopsys DesignWare IP Solutions toolset was embedded into the RTL to backend design flow and verification handoffs. Governance established standardized synthesis constraints, automated synthesis scripts, and project level release gates to ensure consistent area and timing tradeoffs across product variants. The configuration emphasized synthesis and IP integration workflows aligned to Axell Corporation business functions for chip architecture, design, verification and physical implementation.
Baikal Electronics Manufacturing 80 $10M Russia Synopsys Synopsys DesignWare IP Solutions System on Chip Design 2015 n/a
In 2015, Baikal Electronics selected Synopsys DesignWare IP Solutions for System on Chip Design. The procurement covered Synopsys' broad portfolio of DesignWare IP, system-on-chip architecture design and analysis tools, the Galaxy Design Platform, and functional verification products to support development of its advanced SoC designs. Implementation centered on integrating Synopsys DesignWare IP Solutions into Baikal's SoC engineering workflow, providing preverified IP blocks, architecture exploration and analysis capabilities, and a Galaxy Design Platform based implementation and signoff flow. Functional verification products were applied to build verification environments and simulation flows to validate RTL and system-level behavior. Configuration work emphasized IP subsystem integration, timing and power analysis, and verification plan alignment with design milestones. Operational scope focused on Baikal Electronics' SoC design and verification engineering teams based in Russia. The deployment linked architecture and analysis tools with design implementation flows to maintain traceability from system-level models through RTL verification and down to IP integration. The initiative aligned System on Chip Design activities across component IP selection, architecture tradeoffs, and verification orchestration. Governance incorporated centralized IP management and verification process controls to standardize reuse and accelerate iteration across project teams. Synopsys DesignWare IP Solutions served as the core vendor supplied IP and toolset to anchor Baikal Electronics' SoC engineering processes.
iCatch Technology Manufacturing 160 $25M Taiwan Synopsys Synopsys DesignWare IP Solutions System on Chip Design 2015 n/a
In 2015, iCatch Technology implemented Synopsys DesignWare IP Solutions to support development of digital video and image system on chips. The engagement centers on Synopsys DesignWare IP Solutions within the System on Chip Design category and targets integration of silicon proven IP into iCatch Technology's image and video SoC product roadmap. The deployment incorporated Synopsys DesignWare IP Solutions modules typical for video and imaging SoCs, including silicon proven video processing and imaging pipeline IP, interface and PHY IP, and memory controller IP, integrated into SoC RTL and verification flows. Engineering teams configured these IP blocks for reuse in subsystem assembly and to align with standard System on Chip Design practices for IP qualification and integration. Operational coverage focused on iCatch Technology's SoC design and verification organization in Taiwan, with governance oriented around centralized IP management, version control, and formal integration into RTL build and verification pipelines. The implementation positioned Synopsys DesignWare IP Solutions as a foundational IP portfolio embedded in the company's engineering lifecycle for digital video and image SoCs.
Instigate Robotics CJSC Manufacturing 15 $2M Armenia Synopsys Synopsys DesignWare IP Solutions System on Chip Design 2005 n/a
In 2005, Instigate Robotics CJSC implemented Synopsys DesignWare IP Solutions for System on Chip Design. The deployment was executed within the company R&D organization, with workstreams focused on IP module development, RTL implementation, and verification support for a U.S. partner. The implementation included hands on realization of Synopsys DesignWare modules according to vendor data sheets using Verilog HDL, coupled with development of transaction level and SystemC level simulators. Engineering also produced a low level functions library and synthesizable netlists, a parser for a high level device description language, and a TCL API implemented in C++ to support test automation and tool integration. Verification and test automation were anchored by a dejagnu based testsuite using tcl and expect, and the team developed targeted test cases for the company U.S. partner RTL synthesis tools. The Synopsys DesignWare IP Solutions were integrated into this verification flow, and POSIX based sockets and threads libraries were created to support multi thread test harnesses and simulator interfacing. Project governance was run from the R&D group, with scheduled meetings, weekly conference calls with the U.S. partner, resource scheduling, progress updates, and tracking of resource needs. Internal knowledge transfer included courses on POSIX sockets and written functional and development specifications to align development and verification activities.
Aerospace and Defense 97000 $41.0B United States Synopsys Synopsys DesignWare IP Solutions System on Chip Design 2005 n/a
Showing 1 to 6 of 6 entries

Buyer Intent: Companies Evaluating Synopsys DesignWare IP Solutions

ARTW Buyer Intent uncovers actionable customer signals, identifying software buyers actively evaluating Synopsys DesignWare IP Solutions. Gain ongoing access to real-time prospects and uncover hidden opportunities. Companies Actively Evaluating Synopsys DesignWare IP Solutions for System on Chip Design include:

  1. Contract Furniture Professionals, a United States based Professional Services organization with 15 Employees
  2. Global Access Immigration, a United States based Professional Services company with 10 Employees
  3. AGCO Corporation, a United States based Manufacturing organization with 27900 Employees

Discover Software Buyers actively Evaluating Enterprise Applications

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FAQ - APPS RUN THE WORLD Synopsys DesignWare IP Solutions Coverage

Synopsys DesignWare IP Solutions is a System on Chip Design solution from Synopsys.

Companies worldwide use Synopsys DesignWare IP Solutions, from small firms to large enterprises across 21+ industries.

Organizations such as Northrop Grumman, Achronix, Axell Corporation, iCatch Technology and Baikal Electronics are recorded users of Synopsys DesignWare IP Solutions for System on Chip Design.

Companies using Synopsys DesignWare IP Solutions are most concentrated in Aerospace and Defense and Manufacturing, with adoption spanning over 21 industries.

Companies using Synopsys DesignWare IP Solutions are most concentrated in United States, Japan and Taiwan, with adoption tracked across 195 countries worldwide. This global distribution highlights the popularity of Synopsys DesignWare IP Solutions across Americas, EMEA, and APAC.

Companies using Synopsys DesignWare IP Solutions range from small businesses with 0-100 employees - 33.33%, to mid-sized firms with 101-1,000 employees - 50%, large organizations with 1,001-10,000 employees - 0%, and global enterprises with 10,000+ employees - 16.67%.

Customers of Synopsys DesignWare IP Solutions include firms across all revenue levels — from $0-100M, to $101M-$1B, $1B-$10B, and $10B+ global corporations.

Contact APPS RUN THE WORLD to access the full verified Synopsys DesignWare IP Solutions customer database with detailed Firmographics such as industry, geography, revenue, and employee breakdowns as well as key decision makers in charge of System on Chip Design.