List of Synopsys IC Compiler II Customers
Synopsys
675 Almanor Ave,
Sunnyvale, 94085, CA,
United States
Sunnyvale, 94085, CA,
United States
1 650-584-5000
Professional Services
28000
$7.1B
Since 2010, our global team of researchers has been studying Synopsys IC Compiler II customers around the world, aggregating massive amounts of data points that form the basis of our forecast assumptions and perhaps the rise and fall of certain vendors and their products on a quarterly basis.
Each quarter our research team identifies companies that have purchased Synopsys IC Compiler II for Electromigration Simulation and Design from public (Press Releases, Customer References, Testimonials, Case Studies and Success Stories) and proprietary sources, including the customer size, industry, location, implementation status, partner involvement, LOB Key Stakeholders and related IT decision-makers contact details.
Companies using Synopsys IC Compiler II for Electromigration Simulation and Design include: Samsung Electronics, a South Korea based Manufacturing organisation with 262647 employees and revenues of $203.54 billion, Broadcom (inc. VmWare), a United States based Professional Services organisation with 33000 employees and revenues of $63.89 billion, Toshiba, a Japan based Manufacturing organisation with 105331 employees and revenues of $22.26 billion, Graphcore, a United Kingdom based Professional Services organisation with 10 employees and revenues of $1.0 million and many others.
Contact us if you need a completed and verified list of companies using Synopsys IC Compiler II, including the breakdown by industry (21 Verticals), Geography (Region, Country, State, City), Company Size (Revenue, Employees, Asset) and related IT Decision Makers, Key Stakeholders, business and technology executives responsible for the software purchases.
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| Logo | Customer | Industry | Empl. | Revenue | Country | Vendor | Application | Category | When | SI | Insight |
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Broadcom (inc. VmWare) | Professional Services | 33000 | $63.9B | United States | Synopsys | Synopsys IC Compiler II | Electromigration Simulation and Design | 2018 | n/a |
In 2018 Broadcom provisioned Synopsys IC Compiler II for Electromigration Simulation and Design as part of its chip physical design toolset. The implementation was positioned to support physical implementation and timing closure workflows, reflecting noted skills in Static Timing Analysis, PrimeTime, Unix, Physical Design, and Synopsys icc.
Synopsys IC Compiler II was configured to deliver placement, routing, timing driven optimization, and electromigration aware design rule checks consistent with the Electromigration Simulation and Design category. Configuration work emphasized physical synthesis handoff artifacts, timing driven optimization engines, and automated design rule checks that feed into physical closure.
The deployment integrated Synopsys IC Compiler II with static timing analysis using PrimeTime and operated on Broadcom's Unix based engineering compute environment, aligning tool flows with senior STA and physical design engineer practices. Operational coverage focused on Broadcom's physical design and static timing analysis organizations, supporting ASIC implementation and timing signoff functions.
Governance centered on staged adoption by senior STA and physical design teams, formalized handoff processes for timing signoff, and change control for engineering change orders to preserve consistent toolchain runs. Standardization of Unix based run sets and verified timing decks was used to maintain reproducible electromigration analysis and physical verification across the design closure workflow.
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Graphcore | Professional Services | 10 | $1M | United Kingdom | Synopsys | Synopsys IC Compiler II | Electromigration Simulation and Design | 2020 | n/a |
In 2020, Graphcore implemented Synopsys IC Compiler II to support physical design and signoff for its Colossus MK2 GC200 IPU built on a 7nm process node. The UK deployment targeted the multi billion gate AI processor and used Synopsys IC Compiler II as the central RTL to GDS implementation engine.
The implementation leveraged Synopsys IC Compiler II's RTL-to-GDS flow with embedded signoff and power optimization capabilities, features that align with Electromigration Simulation and Design considerations around power network integrity and signoff driven closure. Synopsys IC Compiler II was configured to drive power optimization and signoff iterations as part of the chip delivery pipeline to address manufacturability and reliability constraints typical of advanced node processors.
Operational scope centered on Graphcore's physical implementation and signoff teams in the United Kingdom, impacting chip design, verification, power integrity and signoff workflows. Governance focused on formalizing RTL to GDS handoff processes and embedding the Synopsys IC Compiler II flow into iterative signoff gates. The public outcome reported was first pass silicon success for the Colossus MK2 GC200 IPU achieved using Synopsys IC Compiler II.
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Samsung Electronics | Manufacturing | 262647 | $203.5B | South Korea | Synopsys | Synopsys IC Compiler II | Electromigration Simulation and Design | 2020 | n/a |
In 2020, Samsung Electronics adopted Synopsys IC Compiler II for next-generation 5nm mobile SoC production design in South Korea. Samsung Electronics implemented Synopsys IC Compiler II under the Electromigration Simulation and Design category to support its semiconductor physical implementation flow for mobile SoCs, linking the application to placement, routing and signoff-oriented physical design work.
The deployment leverages the Synopsys IC Compiler II physical implementation and signoff-capable toolset, including machine learning driven placement and routing, timing closure and power optimization capabilities that are core to the product. These modules align with standard physical design workflows and provide automated placement, routing, congestion management and power-aware optimization functions typical for Electromigration Simulation and Design tools.
IC Compiler II was integrated into Samsung's semiconductor physical implementation flow, interfacing with upstream RTL and synthesis outputs and downstream verification and signoff stages to support production tapeout for 5nm mobile SoCs. The operational scope focused on Samsung's semiconductor engineering teams in South Korea and on production-oriented mobile SoC design cycles.
Governance and process changes emphasized embedding IC Compiler II into existing signoff gates and power-aware design checkpoints, enabling engineering teams to adopt tool-driven automation for placement, routing and power optimization. Use of EM-aware design practices is inferred from Synopsys IC Compiler II's signoff and power optimization positioning rather than explicitly stated in the announcement, which is consistent with the Electromigration Simulation and Design category.
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Toshiba | Manufacturing | 105331 | $22.3B | Japan | Synopsys | Synopsys IC Compiler II | Electromigration Simulation and Design | 2015 | n/a |
In 2015 Toshiba deployed Synopsys IC Compiler II in Japan to support physical implementation and tape out of a complex 40nm SoC within its mixed signal IC division, using the application classified in Electromigration Simulation and Design. The deployment focused on a single high complexity SoC project and centered on physical implementation and signoff workflows at the 40 nanometer process node.
Synopsys IC Compiler II was used to drive place and route, timing closure and power optimization activities that align with Electromigration Simulation and Design requirements, with inferred electromigration analysis supported through the tool set's signoff and power integrity capabilities. The implementation emphasized physical implementation capabilities, layout optimization, and signoff oriented checks that are typical of design and electromigration focused flows.
Operationally the work was scoped to Toshiba's mixed signal IC division in Japan and touched core physical design and tape out business functions, integrating the tool into existing physical implementation toolchains without naming specific systems. Governance shifted toward signoff driven flows and tighter physical implementation controls to support the tape out, and the engagement enabled Toshiba to complete the 40nm SoC tape out while proving the toolchain capabilities for future physical implementation efforts.
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Buyer Intent: Companies Evaluating Synopsys IC Compiler II
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FAQ - APPS RUN THE WORLD Synopsys IC Compiler II Coverage
Synopsys IC Compiler II is a Electromigration Simulation and Design solution from Synopsys.
Companies worldwide use Synopsys IC Compiler II, from small firms to large enterprises across 21+ industries.
Organizations such as Samsung Electronics, Broadcom (inc. VmWare), Toshiba and Graphcore are recorded users of
Synopsys IC Compiler II for Electromigration Simulation and Design.
Companies using Synopsys IC Compiler II are most concentrated in Manufacturing and Professional Services, with adoption spanning over 21 industries.
Companies using Synopsys IC Compiler II are most concentrated in South Korea, United States and Japan, with adoption tracked across 195 countries worldwide. This global distribution highlights the popularity of Synopsys IC Compiler II across Americas, EMEA, and APAC.
Companies using Synopsys IC Compiler II range from small businesses with 0-100 employees - 25%, to mid-sized firms with 101-1,000 employees - 0%, large organizations with 1,001-10,000 employees - 0%, and global enterprises with 10,000+ employees - 75%.
Customers of Synopsys IC Compiler II include firms across all revenue levels — from $0-100M, to $101M-$1B, $1B-$10B, and $10B+ global corporations.
Contact APPS RUN THE WORLD to access the full verified Synopsys IC Compiler II customer database with detailed Firmographics such as industry, geography, revenue, and employee breakdowns as well as key decision makers in charge of Electromigration Simulation and Design.