List of ANSYS PathFinder Customers
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Since 2010, our global team of researchers has been studying ANSYS PathFinder customers around the world, aggregating massive amounts of data points that form the basis of our forecast assumptions and perhaps the rise and fall of certain vendors and their products on a quarterly basis.
Each quarter our research team identifies companies that have purchased ANSYS PathFinder for Electrostatic Discharge Simulation (ESD) from public (Press Releases, Customer References, Testimonials, Case Studies and Success Stories) and proprietary sources, including the customer size, industry, location, implementation status, partner involvement, LOB Key Stakeholders and related IT decision-makers contact details.
Companies using ANSYS PathFinder for Electrostatic Discharge Simulation (ESD) include: ST Microelectronics, a Switzerland based Manufacturing organisation with 51370 employees and revenues of $16.13 billion, Western Digital, a United States based Manufacturing organisation with 40000 employees and revenues of $9.52 billion, Altera Corporation, a United States based Professional Services organisation with 2551 employees and revenues of $1.76 billion and many others.
Contact us if you need a completed and verified list of companies using ANSYS PathFinder, including the breakdown by industry (21 Verticals), Geography (Region, Country, State, City), Company Size (Revenue, Employees, Asset) and related IT Decision Makers, Key Stakeholders, business and technology executives responsible for the PLM and Engineering software purchases.
The ANSYS PathFinder customer wins are being incorporated in our Enterprise Applications Buyer Insight and Technographics Customer Database which has over 100 data fields that detail company usage of PLM and Engineering software systems and their digital transformation initiatives. Apps Run The World wants to become your No. 1 technographic data source!
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| Logo | Customer | Industry | Empl. | Revenue | Country | Vendor | Application | Category | When | SI | Insight |
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Altera Corporation | Professional Services | 2551 | $1.8B | United States | Ansys Inc. | ANSYS PathFinder | Electrostatic Discharge Simulation (ESD) | 2012 | n/a |
In 2012, Altera Corporation adopted ANSYS PathFinder for ESD Simulation to support its turn on ESD verification program. Altera implemented ANSYS PathFinder alongside other ESD topology checking tools such as PERC to establish topology-level checks during design signoff.
The implementation centered on topology checking and rule-based net classification to identify turn on ESD risk points, using ANSYS PathFinder for topology visualization and verification workflows. Configuration work focused on embedding topology checks into existing verification runs and creating repeatable rule decks for T/O ESD verification across device IOs and packaging interfaces.
Operationally the ANSYS PathFinder deployment was scoped to design and verification engineering groups responsible for ESD signoff, integrating topology checks into physical verification and signoff gate processes. Governance changes included formalizing topology check steps in verification signoff checklists and scheduling regular runs of PERC and ANSYS PathFinder as part of release validation.
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ST Microelectronics | Manufacturing | 51370 | $16.1B | Switzerland | Ansys Inc. | ANSYS PathFinder | Electrostatic Discharge Simulation (ESD) | 2013 | n/a |
In 2013, ST Microelectronics implemented ANSYS PathFinder to provide ESD Simulation capability for its Imaging Division. The deployment was centered on CAD Tools and flow development for analog and mixed layout and back-end activity, aligning ANSYS PathFinder with the companys CAD toolchain for layout-aware ESD analysis.
ANSYS PathFinder was configured to perform layout driven ESD discharge path extraction and simulation and to feed ESD robustness checks into the physical verification flow. The implementation emphasized functional modules typical of ESD Simulation tools, including extraction of coupling paths from layout, transient discharge modeling and parametric analysis to support layout hardening decisions.
Integrations were explicitly built with existing CAD and verification tooling, including Cadence dvpt development flows, Ansys Totem for detailed ESD waveform analysis, and Mentor Graphics Calibre RealTime for in-layout inspection and signoff feedback. Operational coverage was scoped to the Imaging Division and targeted analog and mixed signal layout engineers and back-end teams responsible for physical verification and signoff.
Governance and process responsibilities were assigned to the team responsible for CAD Tools and flow development, which managed rule sets, runbook updates and the insertion of ESD Simulation checks into standard layout signoff workflows. The implementation positioned ANSYS PathFinder as the ESD Simulation element of ST Microelectronics ANSYS PathFinder ESD Simulation Business Function, ensuring toolchain orchestration and repeatable ESD verification steps within the imaging back-end process.
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Western Digital | Manufacturing | 40000 | $9.5B | United States | Ansys Inc. | ANSYS PathFinder | Electrostatic Discharge Simulation (ESD) | 2015 | n/a |
In 2015, Western Digital implemented ANSYS PathFinder to run Full-Chip ESD analysis. ANSYS PathFinder is deployed as the companys ESD Simulation capability to support IC design verification and reliability engineering workflows.
The implementation focused on full-chip electrostatic discharge analysis, incorporating netlist-aware protection network characterization, automated event-driven ESD simulation, and device-level protection modeling consistent with system-level ESD verification practices. Configuration work emphasized scalable full-chip extraction parameters and hierarchical analysis controls to manage large SoC datasets within ANSYS PathFinder.
ANSYS PathFinder was integrated into IC design verification workflows and existing EDA toolchains to enable iterative ESD checks during late stage design closure. Operational coverage targets on-chip design teams and reliability engineering, where full-chip ESD Simulation runs are executed as part of signoff sequencing and defect mitigation activities.
Governance formalized simulation ownership, defined signoff criteria, and established data version control for full-chip ESD artifacts, aligning ESD Simulation outputs with design release gates and review processes. The rollout emphasized consistent configuration, reproducible simulation setups, and centralized storage of ANSYS PathFinder models and results for auditability.
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Buyer Intent: Companies Evaluating ANSYS PathFinder
- Sony, a Japan based Manufacturing organization with 113000 Employees
Discover Software Buyers actively Evaluating Enterprise Applications
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